1. Field of the Invention
The present invention relates to the technical field of image processing and, more particularly, to an image format conversion system.
2. Description of Related Art
The resolution of video source in a liquid crystal display television (LCD TV) is typically a constant. Accordingly, for a display on different resolution panels, image of a video source has to be scaled for being properly displayed on the different resolution panels. In this case, U.S. Pat. No. 5,739,867 has disclosed an upscaler for a display with an LCD panel.
FIG. 1 is a block diagram of a typical scaler 100. As shown in FIG. 1, the typical scaler 100 essentially replaces frame buffers with line buffers 110, 120, 130. In addition, the operating clocks of deinterlacer 140, FIFO 150, vertical interpolator 160 and horizontal interpolator 170 are generated by applying an image input signal 180 to a frequency multiplier (not shown).
Since the frame buffers are replaced with the line buffers 110, 120, 130, the die size becomes smaller. In addition, because the operating clock is derived from the frequency of the image input signal 180, the phases of the operating clocks of the deinterlacer 140, vertical interpolator 160 and horizontal interpolator 170 have a better synchronization in comparison with the phase of the image input signal 180.
However, due to the line buffers 110, 120, 130 used in the typical scaler, the resolution of the image input signal 180 is limited. Namely, the image input signal 180 must have a horizontal resolution smaller than the available length of the line buffers 110, 120 and 130. Accordingly, the horizontal resolution of the image input signal 180 is gradually increased as the image format is frequently changed, and such a scaler cannot conform with the requirement of scaling operation on an image input signal with a new format.
Further, for electromagnetic interference (EMI) reduction, the clock signal is typically performed with a spread spectrum operation. FIG. 2 is a schematic graph of a typical clock signal spread spectrum. As shown in FIG. 2(A), a clock signal before spreading presents a single-frequency signal in the operating frequency range. As shown in FIG. 2(B), the clock signal after spreading (spreading chips) presents a multi-frequency signal in the operating frequency range, which reduces the amplitude of the clock signal through the spread spectrum technique to thereby reduce the electromagnetic interference. However, owing to the frequency range of the clock signal is widen after spreading, the phase lock loop (PLL) takes more time to lock the frequency of an input signal, and even it cannot lock the frequency of the input signal. In this case, the difficulty in designing the PLL circuitry is thus increased. In addition, when the input signal is unsteady or the frequency range of the clock signal is overlarge after spreading, an abnormal picture possibly occurs.
Therefore, it is desirable to provide an improved image format conversion system to mitigate and/or obviate the aforementioned problems.